? semiconductor components industries, llc, 2006 june, 2006 ? rev. 7 1 publication order number: mc74hc14a/d SN74LS160A bcd decade counters/ 4-bit binary counters the ls160a/161a /162a /163a are high-speed 4-bit synchronous counters. they are edge-triggered, synchronously presettable, and cascadable msi building blocks for counting, memory addressing, frequency division and other applications. the ls160a and ls162a count modulo 10 (bcd). the ls161a and ls163a count modulo 16 (binary). the ls160a and ls161a have an asynchronous master reset (clear) input that overrides, and is independent of, the clock and all other control inputs. the ls162a and ls163a have a synchronous reset (clear) input that overrides all other control inputs, but is active only during the rising clock edge. bcd (modulo 10) binary (modulo 16) asynchronous reset ls160a ls161a synchronous reset ls162a ls163a ? synchronous counting and loading ? two count enable inputs for high speed synchronous expansion ? terminal count fully decoded ? edge-triggered operation ? typical count rate of 35 mhz ? esd > 3500 volts connection diagram dip (top view) note: the flatpak version has the same pinouts (connection diagram) as the dual in-line pack- age. 14 13 12 11 10 9 123456 7 16 15 8 v cc *r tc q 0 q 1 q 2 cet q 3 pe cp p 0 p 1 p 2 p 3 cep gnd *mr for ls160a and ls161a *sr for ls162a and ls163a pin names loading (note a) high low pe p 0 ? p 3 cep cet cp mr sr q 0 ? q 3 tc parallel enable (active low) input parallel inputs count enable parallel input count enable trickle input clock (active high going edge) input master reset (active low) input synchronous reset (active low) input parallel outputs (note b) terminal count output (note b) 1.0 u.l. 0.5 u.l. 0.5 u.l. 1.0 u.l. 0.5 u.l. 0.5 u.l. 1.0 u.l. 10 u.l. 10 u.l. 0.5 u.l. 0.25 u.l. 0.25 u.l. 0.5 u.l. 0.25 u.l. 0.25 u.l. 0.5 u.l. 5 (2.5) u.l. 5 (2.5) u.l. notes: a) 1 ttl unit load (u.l.) = 40 a high/1.6 ma low. b) the output low drive factor is 2.5 u.l. for military (54) and 5 u.l. for commercial (74) temperature ranges. http://onsemi.com bcd decade counters/ 4-bit binary counters low power schottky j suffix ceramic case 620-09 n suffix plastic case 648-08 16 1 16 1 ordering information sn54lsxxxj ceramic sn74lsxxxn plastic sn74lsxxxd soic 16 1 d suffix soic case 751b-03 logic symbol v cc = pin 16 gnd = pin 8 934 56 7 10 2 15 114131211 pe p 0 p 1 p 2 p 3 cep cet cp *r q 0 q 1 q 2 q 3 tc *mr for ls160a and ls161a *sr for ls162a and ls163a
*for the ls162a and * ls163a only. h = high voltage level l = low voltage level x = don?t care SN74LS160A http://onsemi.com 2 state diagram ls160a ? ls162a ls161a ? ls163a 0123 4 5 6 7 8 9 10 11 12 13 14 15 0123 4 5 6 7 8 9 10 11 12 13 14 15 note: the ls160a and ls162a can be preset to any state, but will not count beyond 9. if preset to state 10, 11, 12, 13, 14, or 15, it will return to its normal sequence within two clock pulses. logic equations count enable = cep cet pe tc for ls160a & ls162a = cet q 0 q 1 q 2 q 3 tc for ls161a & ls163a = cet q 0 q 1 q 2 q 3 preset = pe cp + (rising clock edge) reset = mr (ls160a & ls161a) reset = sr cp + (rising clock edge) reset = (ls162a & ls163a) functional description the ls160a / 161a / 162a / 163a are 4-bit synchronous counters with a synchronous parallel enable (load) feature. the counters consist of four edge-triggered d flip-flops with the appropriate data routing networks feeding the d inputs. all changes of the q outputs (except due to the asynchronous master reset in the ls160a and ls161a) occur as a result of, and synchronous with, the low to high transition of the clock input (cp). as long as the set-up time requirements are met, there are no special timing or activity constraints on any of the mode control or data inputs. three control inputs ? parallel enable (pe ), count enable parallel (cep) and count enable trickle (cet) ? select the mode of operation as shown in the tables below. the count mode is enabled when the cep, cet, and pe inputs are high. when the pe is low, the counters will synchronously load the data from the parallel inputs into the flip-flops on the low to high transition of the clock. either the cep or cet can be used to inhibit the count sequence. with the pe held high, a low on either the cep or cet inputs at least one set-up time prior to the low to high clock transition will cause the existing output states to be retained. the and feature of the two count enable inputs (cet ? cep) allows synchronous cascading without external gating and without delay accumulation over any practical number of bits or digits. the terminal count (tc) output is high when the count enable t rickle (cet) input is high while the counter is in its maximum count state (hllh for the bcd counters, hhhh for the binary counters). note that tc is fully decoded and will, therefore, be high only for one count state. the ls160a and ls162a count modulo 10 following a binary coded decimal (bcd) sequence. they generate a tc output when the cet input is high while the counter is in state 9 (hllh). from this state they increment to state 0 (llll). if loaded with a code in excess of 9 they return to their legitimate sequence within two counts, as explained in the state diagram. states 10 through 15 do not generate a tc output. the ls161a and ls163a count modulo 16 following a binary sequence. they generate a tc when the cet input is high while the counter is in state 15 (hhhh). from this state they increment to state 0 (llll). the master reset (mr ) of the ls160a and ls161a is asynchronous. when the mr is low, it overrides all other input conditions and sets the outputs low. the mr pin should never be left open. if not used, the mr pin should be tied through a resistor to v cc , or to a gate output which is permanently set to a high logic level. the active low synchronous reset (sr ) input of the ls162a and ls163a acts as an edge-triggered control input, overriding cet, cep and pe , and resetting the four counter flip-flops on the low to high transition of the clock. this simplifies the design from race-free logic controlled reset circuits, e.g., to reset the counter synchronously after reaching a predetermined value. mode select table *sr pe cet cep action on the rising clock edge ( ) l x x x reset (clear) h l x x load (p n q n ) h h h h count (increment) h h l x no change (hold) h h x l no change (hold)
SN74LS160A http://onsemi.com 3 guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 v t a operating ambient temperature range 54 74 ? 55 0 25 25 125 70 c i oh output current ? high 54, 74 ? 0.4 ma i ol output current ? low 54 74 4.0 8.0 ma ls160a and ls161a dc characteristics over operating temperature range (unless otherwise specified) symbol parameter limits unit test conditions min typ max v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 54 0.7 v guaranteed input low voltage for all inputs 74 0.8 v ik input clamp diode voltage ? 0.65 ? 1.5 v v cc = min, i in = ? 18 ma v oh output high voltage 54 2.5 3.5 v v cc = min, i oh = max, v in = v ih or v il per truth table 74 2.7 3.5 v v ol output low voltage 54, 74 0.25 0.4 v i ol = 4.0 ma v cc = v cc min, v in = v il or v ih per truth table 74 0.35 0.5 v i ol = 8.0 ma i ih input high current mr , data, cep, clock pe , cet 20 40 a v cc = max, v in = 2.7 v mr , data, cep, clock pe , cet 0.1 0.2 ma v cc = max, v in = 7.0 v i il input low current mr , data, cep, clock pe , cet ? 0.4 ? 0.8 ma v cc = max, v in = 0.4 v i os short circuit current (note 1) ? 20 ? 100 ma v cc = max i cc power supply current total, output high total, output low 31 32 ma v cc = max note 1: not more than one outpu t should be shorted at a time, nor for more than 1 second.
SN74LS160A http://onsemi.com 4 ls162a and ls163a dc characteristics over operating temperature range (unless otherwise specified) symbol parameter limits unit test conditions min typ max v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 54 0.7 v guaranteed input low voltage for all inputs 74 0.8 v ik input clamp diode voltage ? 0.65 ? 1.5 v v cc = min, i in = ? 18 ma v oh output high voltage 54 2.5 3.5 v v cc = min, i oh = max, v in = v ih or v il per truth table 74 2.7 3.5 v v ol output low voltage 54, 74 0.25 0.4 v i ol = 4.0 ma v cc = v cc min, v in = v il or v ih per truth table 74 0.35 0.5 v i ol = 8.0 ma i ih input high current data, cep, clock pe , cet, sr 20 40 a v cc = max, v in = 2.7 v data, cep, clock pe , cet, sr 0.1 0.2 ma v cc = max, v in = 7.0 v i il input low current data, cep, clock, pe , sr cet ? 0.4 ? 0.8 ma v cc = max, v in = 0.4 v i os short circuit current (note 1) ? 20 ? 100 ma v cc = max i cc power supply current total, output high total, output low 31 32 ma v cc = max note 1: not more than one outpu t should be shorted at a time, nor for more than 1 second. ac characteristics (t a = 25 c) symbol parameter limits unit test conditions min typ max f max maximum clock frequency 25 32 mhz v cc = 5.0 v c l = 15 pf t plh t phl propagation delay clock to tc 20 18 35 35 ns t plh t phl propagation delay clock to q 13 18 24 27 ns t plh t phl propagation delay cet to tc 9.0 9.0 14 14 ns t phl mr or sr to q 20 28 ns ac setup requirements (t a = 25 c) symbol parameter limits unit test conditions min typ max t w cp clock pulse width low 25 ns v cc = 5.0 v t w mr or sr pulse width 20 ns t s setup time, other* 20 ns t s setup time pe or sr 25 ns t h hold time, data 3 ns t h hold time, other 0 ns t rec recovery time mr to cp 15 ns *cep, cet, or data
SN74LS160A http://onsemi.com 5 definition of terms setup time (t s ) ? is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from low to high in order to be recognized and transferred to the outputs. hold time (t h ) ? is defined as the minimum time following the clock transition from low to high that the logic level must be maintained at the input in order to ensure continued recognition. a negative hold time indicates that the correct logic level may be released prior to the clock transition from low to high and still be recognized. recovery time (t rec ) ? is defined as the minimum time required between the end of the reset pulse and the clock transition from low to high in order to recognize and transfer high data to the q outputs. ac waveforms figure 1. clock to output delays, count frequency, and clock pulse width figure 2. master reset to output delay, master reset pulse width, and master reset recovery time 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v cp q t w (h) t w (l) t rec t phl t phl t plh other conditions: pe = mr (sr ) = h cep = cet = h other conditions: pe = l p 0 = p 1 = p 2 = p 3 = h t w q 0 q 1 q 2 q 3 mr cp
SN74LS160A http://onsemi.com 6 figure 3 the positive tc pulse occurs when the outputs are in the (q 0 ? q 1 ? q 2 ? q 3 ) state for the ls160 and ls162 and the (q 0 ? q 1 ? q 2 ? q 3 ) state for the ls161 and ls163. other conditions: cp = pe = cep = mr = h 1.3 v t phl t plh 1.3 v 1.3 v 1.3 v cet tc ac waveforms (continued) the positive tc pulse is coincident with the output state (q 0 ? q 1 ? q 2 ? q 3 ) state for the ls161 and ls163 and (q 0 ? q 1 ? q 2 ? q 3 ) for the ls161 and ls163. figure 4 other conditions: pe = cep = cet = mr = h 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v t plh t phl cp tc the shaded areas indicate when the input is permitted to change for predictable output performance. figure 5 1.3 v 1.3 v other conditions: pe = l, mr = h cp 1.3 v 1.3 v 1.3 v t s (h) t s (l) t h (h) = 0 t h (l) = 0 q 0 q 1 q 2 q 3 p 0 p 1 p 2 p 3 other conditions: pe = h, mr = h 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v t s (h) t s (l) t h (h) = 0 t h (l) = 0 t s (h) t h (h) = 0 t s (l) t h (l) = 0 count hold hold cep cp cet q cp sr or pe q response to pe reset count or load q response to sr parallel load (see fig. 5) count mode (see fig. 7) t s (l) t s (h) t h (l) = 0 t h (h) = 0 1.3 v 1.3 v figure 6 count enable trickle input to terminal count output delays clock to terminal count delays setup time (t s ) and hold time (t h ) for parallel data inputs setup time (t s ) and hold time (t h ) for count enable (cep) and (cet) and parallel enable (pe ) inputs figure 7 the shaded areas indicate when the input is permitted to change for predictable output performance. 1.3 v
SN74LS160A http://onsemi.com 7 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 SN74LS160A/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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